Espressif Systems /ESP32-S3 /UHCI0 /INT_ST

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Interpret as INT_ST

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_START_INT_ST)RX_START_INT_ST 0 (TX_START_INT_ST)TX_START_INT_ST 0 (RX_HUNG_INT_ST)RX_HUNG_INT_ST 0 (TX_HUNG_INT_ST)TX_HUNG_INT_ST 0 (SEND_S_REG_Q_INT_ST)SEND_S_REG_Q_INT_ST 0 (SEND_A_REG_Q_INT_ST)SEND_A_REG_Q_INT_ST 0 (OUTLINK_EOF_ERR_INT_ST)OUTLINK_EOF_ERR_INT_ST 0 (APP_CTRL0_INT_ST)APP_CTRL0_INT_ST 0 (APP_CTRL1_INT_ST)APP_CTRL1_INT_ST

Description

Masked interrupt status

Fields

RX_START_INT_ST

This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1.

TX_START_INT_ST

This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1.

RX_HUNG_INT_ST

This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1.

TX_HUNG_INT_ST

This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1.

SEND_S_REG_Q_INT_ST

This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1.

SEND_A_REG_Q_INT_ST

This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1.

OUTLINK_EOF_ERR_INT_ST

This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1.

APP_CTRL0_INT_ST

This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1.

APP_CTRL1_INT_ST

This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1.

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